Asic / Layout Design Engineer Resume Sample
Clinton Bergstrom
15728 Nicolas Passage,
Dallas,
TX
+1 (555) 357 6353
Work Experience
Senior Asic / Layout Design Engineer
07/2017
-
PRESENT
Houston, TX
- Experience with process and methodology improvements to enhance verification productivity
- Predict the scope of verification tasks and set priorities for effective verification
- ASIC design and verification experience and deep knowledge of GPU.
- Proven experience of the latest design verification methodology such as assertion coverage based driven verification (code & functional coverage), constraint random test generation, and familiar with the latest languages such as SystemVerilog, UVM/OVM, SystemC/C++,SVA,
- In depth knowledge of ASIC design fundamentals
- Good people and project management skills and organized and methodical with proven ability to plan and execute
- Work well in a dynamic, fast-paced, pressure filled environment
- SoC DV testbench and infrastructure development and maintenance
- Implement directed and random test cases in C++/SV, as well as checkers and assertions
MTS Asic / Layout Design Engineer
10/2010
-
03/2017
Dallas, TX
- MS with 3+ or BS with 5+ years’ experience in ASIC/SoC design verification
- Hand-on experience of complex ASIC DV flow from plan to coverage
- Knowledgeable in C++ & SV development, familiar with scripting languages like Ruby/Perl/Makefile…
- Experience in power-aware verification is an asset
- Development and execution of pre-silicon verification test plans
- Development of verification environment and infrastructure
- Verification of complex microprocessor SOC's
- Development of directed and random verification tests to validate IP/chip function
- Debug of Verilog RTL and gate-level simulation, at the IP and/or chip-level
Asic / Layout Design Engineer
07/2005
-
09/2010
Los Angeles, CA
- Knowledge of industry standard simulation tools (VCS, Verdi)
- Verification functional coverage using industry standard coverage analysis tools/methods
- Replicate functional issues found post-silicon; review/enhance tests to verify bug fixes
- BSEE + 2+ years industry experience in HW functional verification, on processor or graphics chips
- Strong programming skills in C, Perl, Ruby
- Computer architecture, processor microarchitecture
- Familiarity with RISC or CISC level instruction sets, memory ordering, interrupts, MMU, caches and coherency rules
- Experience in IP or Soc Design Verification, with knowledge of Computer Architecture
Education
The University of Kansas
2001 - 2005
Engineer's Degree in Electrical
Professional Skills
- + Strong analytical thinking and problem solving skills, excellent attention to detail, and good coding skills and style required
- Strong analytical thinking and problem solving skills, excellent attention to detail, and good coding skills and style required
- Good communication skills, strong interpersonal skills and the flexibility, experience on leading team
- Experience with scripting is highly recommended - Requires strong Programming and debug skills
- Experience scripting languages is highly recommended - Requires strong Programming and debug skills
- Strong experience on C/C++ language with demonstrable C/C++ programming skills
- High proficiency in C programming & demonstrated examples of strong skills
How to write Asic / Layout Design Engineer Resume
Asic / Layout Design Engineer role is responsible for programming, analytical, english, interpersonal, software, engineering, coding, debug, teamwork, leadership.
To write great resume for asic / layout design engineer job, your resume must include:
- Your contact information
- Work experience
- Education
- Skill listing
Contact Information For Asic / Layout Design Engineer Resume
The section contact information is important in your asic / layout design engineer resume. The recruiter has to be able to contact you ASAP if they like to offer you the job. This is why you need to provide your:
- First and last name
- Telephone number
Work Experience in Your Asic / Layout Design Engineer Resume
The section work experience is an essential part of your asic / layout design engineer resume. It’s the one thing the recruiter really cares about and pays the most attention to.
This section, however, is not just a list of your previous asic / layout design engineer responsibilities. It's meant to present you as a wholesome candidate by showcasing your relevant accomplishments and should be tailored specifically to the particular asic / layout design engineer position you're applying to.
The work experience section should be the detailed summary of your latest 3 or 4 positions.
Representative Asic / Layout Design Engineer resume experience can include:
- Strong post-silicon skills and lab bringup experience
- Strong experience on Matlab/C++/C language with demonstrable Matlab/C++/C programming skills
- Strong RTL analysis skills including Verilog, Timing Analysis and library understanding
- Demonstrated modeling skills in C/C++
- Strong analytical and problem solving skills along with attention to details
- Self-motivated and excellent problem solving skills
Education on an Asic / Layout Design Engineer Resume
Make sure to make education a priority on your asic / layout design engineer resume. If you’ve been working for a few years and have a few solid positions to show, put your education after your asic / layout design engineer experience. For example, if you have a Ph.D in Neuroscience and a Master's in the same sphere, just list your Ph.D. Besides the doctorate, Master’s degrees go next, followed by Bachelor’s and finally, Associate’s degree.
Additional details to include:
- School you graduated from
- Major/ minor
- Year of graduation
- Location of school
These are the four additional pieces of information you should mention when listing your education on your resume.
Professional Skills in Asic / Layout Design Engineer Resume
When listing skills on your asic / layout design engineer resume, remember always to be honest about your level of ability. Include the Skills section after experience.
Present the most important skills in your resume, there's a list of typical asic / layout design engineer skills:
- Good English hearing, speaking, reading and writing capabilities and good communication skills
- Strong communication and collaboration skills. Experience working in large multi-site engineering organizations
- Strong experience on C/C++/Matlab language with demonstrable C/C++/Matlab programming skills
- Strong analysis, problem solving and reporting skills
- Strong debugging & testing skills
- Strong collaboration skills across multiple geographies interacting with AMD global teams
List of Typical Experience For an Asic / Layout Design Engineer Resume
1
Experience For MTS Asic / Layout Design Engineer Resume
- Excellent attention to detail with great coding skills with respect to accuracy, debug ability, build and runtime performance, reuse
- Proven hands-on design and DV experiences are good assets
- Strong experience working with Cadence NCSIM, Synopsys VCS or equivalent
- Strong Experience working with UVM, OVM or equivalent
- Proven verification experience on large ASIC development projects
- Video codec experience is a good asset
2
Experience For Senior Asic / Layout Design Engineer Resume
- Good team player and strong sense of responsibility
- Strong C/C++ and Matlab development experience
- MSEE or MSCE with 2 years of experience or BSEE/BSCS with 5 years of experience in ASIC Physical Design from RTL to GDSII
- Verificaiotn Testbench understanding and working experience
- Represent GMHUB design team in post-silicon platforms for feature list delivery, bring-up and validation test planning and post-silicon debug
- Experience with standard ASIC design tools (synthesis, simulation, equivalence checking, static timing analysis)
3
Experience For Smts Asic / Layout Design Engineer Resume
- Strong scripting language expertise
- Experience with UVM, hardware modeling, assertions, and formal verification methods
- Excellent understanding of computer architecture, hardware concepts & design tradeoffs required
- Experience on synthesis, timing analysis, CDC and formal verification
- Hands-on experience on building system level testbench from scratch
4
Experience For Pmts Asic / Layout Design Engineer Resume
- Good understanding on verilog, systemverilog, c, c++, Pli, Dpi, Perl
- Direct experience in high speed digital design using Verilog
- Experience with Perl, Ruby, and Scripting languages highly desired
- Hands-on experience in modeling for verification, architecture analysis, and performance characterization
- Demonstrated ability to work cross-functionally with independent problem solving
- Strong understanding of SOC architecture
- Work very closely with physical design engineers to help on floorplan, timing closure, power design validation and etc
- Demonstrate expertise in the following
5
Experience For Senior Asic Layout / Design Engineer Resume
- Working experience on ASIC design
- Experience using industry standard tools and adoptability to utilize home grown tools
- Be good at both speaking and written English
- Debug of IP and SOC issues found during pre-silicon, bringup, validation, and production phases of SOC programs
- Significant experience with Verilog, Object-Oriented Programming and hands-on lab expertise are a requirement
- Significant experience with C/C++, Verilog, System Verilog, and Object-Oriented Programming expertise are a requirement
- Industry experience using advanced verification methodologies such as UVM or VMM
- Strong understanding of digital ciruit design and verifications
- Good understanding of computer and graphics organization/architecture
6
Experience For Experienced Asic / Layout Design Engineer Resume
- Good understanding of full chip PD signoff guidelines is an asset
- Strong understanding of high speed high performance digital designs
- 4 Hands on experience in taping out 14nm, 16nm, 20nm, 28nm, 32nm, and/or 40nm SOC
- Creative and good at solving problems
- Strong knowledge of clock domain crossing
- Experience on power-aware synthesis, VC-LINT, CDC tool, clock definition, writing design constraints
- Strong understanding of video codecs such as H.264/AVC & H.265/HEVC & VP9 is highly desirable
- Or more years of experience in RTL coding or DV or Synthesis-PD in digital ASIC chips
- MS with 10+ or BS with 12+ years' experience in ASIC/SoC design verification
7
Experience For Asic / Layout Design Engineer Contractor Resume
- Hand-on experience in all domains of complex ASIC DV flow from plan to coverage, both
- Experience working with UVM, OVM or equivalent
- Experience with scripting languages, Ruby/Python/Tcl/BASH/etc
- Drive silicon debug, validation, and characterization of NBIO IPs across SOC products
- Work with cross organization teams to ensure Silicon/SW/Platform/etc. features are in sync, development is supported, and validation is planned
8
Experience For Smts DFT Asic / Layout Design Engineer Resume
- Defect prioritization and root-cause resolution plans
- Drive solid solutions to technical issues and design challenges
- Identify & Root-cause failures found in SoC Validation and Characterization
- Debug any IP related open sightings reported by platform validation team and customers
- Experience with Verilog, C/C++, SVA/PSL required
- Experience with, and creation of, constrained random testbenches required
- Familiar with Verilog RTL design and has experience of digital ASIC project
9
Experience For Engineer Asic / Layout Design Engineer Resume
- Relevant ASIC DV experience
- Video DV experience is highly desired
- Over 8 years experience with BSEE/BSCS or 5+ years of MSEE or MSCE in ASIC Physical Design from RTL to GDSII
- Experience with C/C++, Verilog required
- Experience with BSEE/BSCS or MSEE or MSCE in ASIC Physical Design from RTL to GDSII
10
Experience For Principal Asic / Layout Design Engineer Resume
- Direct design experience with C++
- Over 6 years experience with MSEE or MSCE in ASIC Physical Design from RTL to GDSII
- ASIC design and verification experience and deep knowledge of GPU.
- MS +3 years, BS +5 years relative experience
- Experience in system performance and power analysis
- Power/thermal management experience is an asset
- Experience in system end-to-end control/data flow that includes drivers/software
List of Typical Skills For an Asic / Layout Design Engineer Resume
1
Skills For MTS Asic / Layout Design Engineer Resume
- Strong individual analysis, problem solving skills and teamwork attitude
- Excellent programming skills, proficient in C/C++, SystemVerilog
- Self-motivated, leadership skills and experience working with global teams
- Demonstrated programming skills in C/C++
- Team player with good interaction skills
- Good written skills for documentation
2
Skills For Senior Asic / Layout Design Engineer Resume
- Industry design/verification EDA tools expertise. Strong software skills
- Excellent Block level and Full-chip physical design skills
- + Excellent communication and interpersonal skills both verbal and written for interaction with a large team across multiple sites
- Good verbal & written communication, organization, analytical and leadership skills
- Good verbal & written communication, organization, analytical and leadership skills are essential
- Hands on working experience on ASIC design and/or verification and/or testing/validation
- Hands on working experience on ASIC design and/or verification and/or testing/validation is desired
- Proven verification experience on large ASIC development projects in a hardware development setting
3
Skills For Smts Asic / Layout Design Engineer Resume
- Excellent knowledge and experience on design techniques and Front end tools for synthesis, timing etc.
- Prior development experience of GPU/CPU performance and/or power modeling and infrastructure
- Excellent programming skill, proficient in MySQL/PostgreSQL, HTML, Javascript, C++
- Prior experience with graphics design/pipelining is required
- Experience in Verilog, scripting experience (csh, perl, awk, etc.)
- Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language,OVM/UVM Methodology knowledge and experience
- Strong RTL (Verilog) experience
- Engineers with 2-5 years industry experience in ASIC RTL Design and logic design experience
4
Skills For Pmts Asic / Layout Design Engineer Resume
- Experience in physical design, tapeout experience in 28nm or advanced process
- BS-CS/BS-EE with at least 7 years' experience or MS with at least 5 years' experience in ASIC/SoC design
- BS-CS/BS-EE with at least 5 years' experience or MS with at least 3 years' experience in SW/FW development
- BS-CS/BS-EE with at least 5 years' experience or MS with at least 3 years' experience in ASIC/SoC design
- Excellent communication skill and self-study capability. Can work independently and initiatively
- Prior hands-on experience in database development
- M.S. with more than 4 years of applicable experience or PhD with applicable experience,
- Be good at communication and teamwork, self-motivated and with good work ethics
- + Teamwork and interpersonal skills
5
Skills For Senior Asic Layout / Design Engineer Resume
- Strong understanding of hardware principles including verilog, preferably with previous experience
- BS-CS/BS-EE with at least 7 years' experience or MS with at least 5 years' experience in multimedia domain
- Strong multimedia/video/camera related system level knowledge and experience
- Proven ASIC design experience
- Able to effectively communicate via emails/telephone with block teams in other sites
- Strong communication skill and cross-site team work is desired
- Strong and clear communication skill, fluent in English are required
- Strong skill on Verilog / SV, C/C++, and UVM knowledge
6
Skills For Experienced Asic / Layout Design Engineer Resume
- Experience architecting/developing complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar
- Hands-on coding and debugging experience in a challenging work environment
- Have an in depth understanding and experience for leading all Physical Design activities for a large, leading technology SOC ASIC chip
- Strong knowledge of modern OS kernel (MS, Linux) and programming / scripting language (C/C++, Python, Perl, …
- Experience with low level, physical phenomena oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.)
- Strong RTL coding with Verilog, test-bench coding with SystemVerilog
- Solid knowledge of ASIC/SOC design flow, including coding, simulation, verification, synthesis and STA
- Graphics processing RTL coding & DV experience is highly desired
7
Skills For Asic / Layout Design Engineer Contractor Resume
- Experience with low level, physical phenomena oriented logic design is an asset (dealing with IO, clocking, voltage control, DFT, etc.)
- Graphics processing RTL coding and DV experience is highly desired
- Validate design qaulity including CDC (clock domain crossing) , LINT checks
- Strong understanding of industry standard IO interfaces(SATA, USB, PCIe, XGbE, IOMMU)
- Experience working with Synopsys VCS and waveform viewers
- Experience developing cycle-accurate hardware models in a high-level language, such as C++
- Experience in GPGPU programming (CUDA/OpenCL)
8
Skills For Smts DFT Asic / Layout Design Engineer Resume
- Experience in deep learning frameworks such as Caffe, TensorFlow
- Experience in Machine Learning APIs, frameworks, and AI tools
- Experience in array cameras, computational photography techniques, depth sensing cameras and others
- Experienced in UVM based testbenches, drivers, monitors, assertions, and debugging in these environments
- Prior exposure to Memory Bist, AMBA AXI, Power gating, ATPG scan
- PhD in Electrical or Computer Engineering with at least 5 years of work experience or
- Master in Electrical or Computer Engineering with at least 7 years of work experience or
- Strong understanding of modern chip design flows
9
Skills For Engineer Asic / Layout Design Engineer Resume
- Working experience on ASIC design or verification
- Working experience on ASIC design verification
- Industry experience using advanced verification methodologies such as UVM or VMM is an asset
- Very strong background in C/C++ coding techniques
- Strong knowledge of UNIX/Linux operating systems and debug tools
- Strong understanding of digital and analog electronics
- Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager
10
Skills For Principal Asic / Layout Design Engineer Resume
- Good Understanding of dGPU SOC architecture
- Experience with Building test bench and monitors for DUT
- Have more than 3-year experience in C++/OpenGL/OpenCL/DX programing
- Good understanding of computer organization/architecture
- Laboratory experience, including the use of equipment: oscilloscopes, logic analyzers, etc
List of Typical Responsibilities For an Asic / Layout Design Engineer Resume
1
Responsibilities For MTS Asic / Layout Design Engineer Resume
- Proven track record of architecting, developing, and shipping complex silicon and systems
- Familiar with entire ASIC design flow, hands on working experience on ASIC DFT design and verification is an advantage
- Hands on experience in taping out 14nm, 16nm, 20nm, 28nm, 32nm, and/or 40nm SOC
- Strong knowledge of C++ and object oriented programming
- Strong understanding of digital electronics
2
Responsibilities For Senior Asic / Layout Design Engineer Resume
- Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC
- Experience of working on Functional Verification, SoC Verification, Emulation
- Preferably having experience in architecture such as x86 or ARM domain based SOCs
- Experience with logic synthesis or physical design or semiconductor physics or system design
- Knowledge on the low power design and optimization or lab experience
- A good Team player who learns and thrives in team settings
- ASIC design and verification experience and deep knowledge of GPU.
- Participate in pre (Emulation) and post silicon validation and make sure wi-fi/BT feature works
- Experience with Architectural participation
3
Responsibilities For Smts Asic / Layout Design Engineer Resume
- Experience on WLAN and BT for 2 generations
- Familiar with Verilog RTL design and has experience of large digital ASIC project
- Hands-on experience in Verilog and System Verilog logic design and design verification
- A good Team player who learns and thrives in a team settings
- Be good at script language, such as Perl, Python, Ruby, C Shell, Makefile
- Developing and maintaining complex verification environments using various methodologies, including
- Defining/Writing/Implementing Test Plans and Strategy/Methodology Documents
- Writing, Modifying, and Maintaining Random and Directed Test Cases and Libraries in SystemVerilog/UVM
4
Responsibilities For Pmts Asic / Layout Design Engineer Resume
- Compiling, updating and maintaining block level micro architectural specification
- Reproducing and debugging problems reported and identifying solutions
- Making full use of leading-edge synthesis, static timing analysis, and formal verification methods
- Capturing high-quality RTL meeting functional, timing, & power requirements
- Working with Graphics Architects and Design Team members to Understand and Refine Forward-Looking graphics features
5
Responsibilities For Senior Asic Layout / Design Engineer Resume
- Architecting and Developing Testbenches and Verification Components such as UVCs, models, BFMs, and Re-usable Verification Environments
- Deploying Industry-Leading Verification Methodologies such as UVM, and Formal Verification
- Triaging and Debugging complex Regressions
- Architecting and defining strategy for hardware and firmware co-verification
- Running and analyzing synthesis and power analysis flows
- Leading the Team's development of leading edge innovative IP level features
- Assisting in debug and resolution of post-silicon issues involving firmware
6
Responsibilities For Experienced Asic / Layout Design Engineer Resume
- Defining and executing the overall functional test plan and verification strategy for a set of AMD IP and SOC’s
- Leading & mentoring a focused design & DV sub-team
- Resolving silicon bring-up design issues
- Enhancing and designing test libraries
- Working knowledge of UNIX/Linux operating systems and debug tools
7
Responsibilities For Asic / Layout Design Engineer Contractor Resume
- Writing firmware for embedded u-controllers in C as required
- Conferring with RTL Designers and SOC DV Leads on Verification Requirements and Methodologies
- Assessing Assertions and Functional Coverage
- Reproducing Functional Bugs found in Silicon in Simulation and/or Formal Verification tools
- Working knowledge of cache structures and virtual memory management is an assert
- Writing Area/Power optimized Verilog RTL Code
8
Responsibilities For Smts DFT Asic / Layout Design Engineer Resume
- Utilizing In-House and 3rd Party IP/SOC CAD and EDA Tools specifically for ASIC Design
- Scripting to automate processes
- Leading a small team of engineers
- Optimizing FW code to improve performance
- Leading execution of all graphics blocks for a high-end graphics part
- Bring post-silicon knowledge to drive improvements in pre-silicon processes
9
Responsibilities For Engineer Asic / Layout Design Engineer Resume
- Working knowledge of memory and memory controller design, cache structures and virtual memory management is an asset
- Working with architects & customers to develop specifications
- Writing design specifications & DV test plans
- Designing sophisticated low-power & high-speed RTL IP from scratch (arbiters, FIFOs, FSMs, TLB, caches, ...)
- Linting RTL and clock-domain crossings
- Coding test-benches to verify the design
- Writing test stimulus for 100% functional & code coverage
- Modelling the design in C++
- Emulating the design on FPGA-based systems
10
Responsibilities For Principal Asic / Layout Design Engineer Resume
- Working with other leads to develop practical schedules
- Participating in the pre-silicon verification for full chip, blocks, multi-chip and system level
- Working with all stakeholders such as lead architects and block design teams to understand features to be implemented and verified
- Monitoring test cases in regressions
- Looking at the RTL to find functional bugs,
- Working with the RTL team to fix the bugs,
- Reading the AMD Memory Controller MAS(micro-architectural Spec) and Jedec DRAM Guidelines (ddr4/lpddr4/lpddr5//ddr5/NVDIMM-p) and DFI (Dram Phy Interface Spec)
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