Logic Design Engineer Resume Sample
Isaias Adams
596 Brandi Points,
Boston,
MA
+1 (555) 557 2748
Work Experience
Senior Logic Design Engineer
06/2016
-
PRESENT
San Francisco, CA
- BS (or higher) in EE /Computer Engg. with 7-10 years of relevant experience
- Excellent logic design skills as demonstrated by successful ASIC or SoC implementations
- MS or BS (or higher) in EE /Computer Engg. with 3-5 years of relevant experience
- Experience in logic design. good knowledge of design flows and tools. Ethernet protocols knowledge - advantage.Good knowledge with VerilogExperience with link layer/PCS protocol such as DisplayPort, HDMI, USB, PCIe, SATA – Advance
- Strong analytical and debugging skill, and creative in problem-solving
- Develop timing constraints working closely with the IP Vendor or the Customer Engineering Team
- Develop fully automated environment for implementation allowing for integration of the IP at system level with any set of parameters
Logic Design Engineer
06/2011
-
01/2016
Houston, TX
- Take on large responsibilities and lead a group of engineers
- Debug, fix, and validate pre- and post-silicon power management sub-system logic issues and RTL bugs
- Good written/verbal communication skills and strong teamwork
- Configure and verify complex IP and integrate into an effective
- Design functional logic including chip level clock and reset controllers Synthesize RTL to meet timing requirements and verify logical
- BS and 8+ years of experience, MS and 7 years of experience
- To assist with the design, development, and testing of microprocessor-based
- Working with SOC/ASIC team defining, architecting and development of RTL blocks
- Working with IP teams and integration of IP
Junior Logic Design Engineer
02/2005
-
05/2011
San Francisco, CA
- As part of IP scale-ability efforts, define a well-known and documented structure for IP implementation so it can easily be ported to any new cores
- Provide support for closing timing of the IP at full chip level and work with the IP Vendor to optimize the code for ASIC implementation
- Improve the IP Implementation Checklist to minimize timing closure duration and avoid iterations at full chip level
- Experience in logic design
- Experience, ideally in processor or other related high performance designs
- Solid understanding of physical design and VLSI
- Top notch communication skills
- Some background in computer architecture is desirable
Education
Florida State University - Panama City Campus
2001 - 2005
Engineer's Degree in Electrical Engineering
Professional Skills
- Strong written and verbal communication skills, including presentation, training, and mentoring
- Experience in HDL programming experience SV or Verilog or VHDL2+ years of experience in BE tools synthesis, timing, routing, placement etc
- Experience in the following areas/ skills
- Work closely with Validation Architect in defining validation strategy and reviewing testplan
- Experience with logic design and validation tools and methodologies including: Verilog , System Verilog , SVA, Synopsis VCS
- Strong programming skill in System Verilog, Perl, C++ or etc
- Strong experience/background in RTL level Digital IC Design using System Verilog and/or Verilog
How to write Logic Design Engineer Resume
Logic Design Engineer role is responsible for design, programming, analytical, digital, architecture, verilog, logic, debugging, teamwork, timing.
To write great resume for logic design engineer job, your resume must include:
- Your contact information
- Work experience
- Education
- Skill listing
Contact Information For Logic Design Engineer Resume
The section contact information is important in your logic design engineer resume. The recruiter has to be able to contact you ASAP if they like to offer you the job. This is why you need to provide your:
- First and last name
- Telephone number
Work Experience in Your Logic Design Engineer Resume
The section work experience is an essential part of your logic design engineer resume. It’s the one thing the recruiter really cares about and pays the most attention to.
This section, however, is not just a list of your previous logic design engineer responsibilities. It's meant to present you as a wholesome candidate by showcasing your relevant accomplishments and should be tailored specifically to the particular logic design engineer position you're applying to.
The work experience section should be the detailed summary of your latest 3 or 4 positions.
Representative Logic Design Engineer resume experience can include:
- Motivated, self-directed and able to work effectively both independently and with team
- Experience – experience 7+ years
- Experience in VLSI or Structural and Physical design flow/methodology.-Experience in PCI express or any Industrial standard bus protocol would be added value
- Good leadership, interpersonal and communication skill
- Working on FPGA emulations, and design validation using FPGAs & Emulation flow
- Understanding of PCI Express architecture and have experience in PCI Express microarchitecture
Education on a Logic Design Engineer Resume
Make sure to make education a priority on your logic design engineer resume. If you’ve been working for a few years and have a few solid positions to show, put your education after your logic design engineer experience. For example, if you have a Ph.D in Neuroscience and a Master's in the same sphere, just list your Ph.D. Besides the doctorate, Master’s degrees go next, followed by Bachelor’s and finally, Associate’s degree.
Additional details to include:
- School you graduated from
- Major/ minor
- Year of graduation
- Location of school
These are the four additional pieces of information you should mention when listing your education on your resume.
Professional Skills in Logic Design Engineer Resume
When listing skills on your logic design engineer resume, remember always to be honest about your level of ability. Include the Skills section after experience.
Present the most important skills in your resume, there's a list of typical logic design engineer skills:
- Strong Automation and Scripting Development Skills (PERL, TCL or Python)
- Strong programming skill in Perl/Tcl is desirable
- Exceptional communication skills and ability to work as part of a team
- An ability to work effectively and drive action across hardware and software teams
- Experience – 11+ years of related work experience required
- Experience – 4+ years of relevant work experience
List of Typical Experience For a Logic Design Engineer Resume
1
Experience For IP Logic Design Engineer Resume
- Experience in the last 3 years working with validation engineers to develop functional validation and coverage test plans
- Experience in unit level validation environment development, test plan generation and test case implementation for the verification of design blocks
- Mixed Signal Design or Validation Experience
- Overall experience performing Register Transfer Level (RTL) logic design using System Verilog
- Experience in the last 3 years with RTL development, design partitioning, micro-architecture trade-offs and knowledge in timing closure
- Experience in one or more scripting languages such as Python, Perl or Tcl
- Demonstrated leadership in networking hardware design
- Demonstrated leadership in networking fabric switch/NIC design
- Experience with languages and standards such as Verilog, System Verilog, Perl, Shell scripting, UPF, OCP, PCIe, IOSF, UPF2.0
2
Experience For Senior Logic Design Engineer Resume
- Good level of understanding of BE constrains and MOW - advantage
- Experience running STA flows
- Hands on experience with Cadence, Synopsys & Mentor EDA tools
- Experience with at least one of Serial protocols (PCIe, USB or SATA)
- Experience in frontend design
- Strong demonstration to able to work well with each other towards common goals, aligned with career development
- Familiarity in IP development Tools, Validation TFM and collaterals
- Experience in System Verilog, OVM/UVM, RTL development for high performance and low power design
3
Experience For Senior IP Logic Design Engineer Resume
- Experience in System Verilog, OVM and Architecture Spec definition
- Experience with High Speed I/O Design
- Experience with CDC, Lint, UPF, or GLS
- BSc in EE / CE from top Israeli universities- 1-2 years of experience
- Past industry experience in IP logic design
- Timing verification using Synopsys Prime-Time as well as Intel tools
- Working knowledge of Synthesis and Static Timing Analysis STA with Design Compiler and Primetime
- Working closely with silicon architect and micro-architect in design definition and implementation
4
Experience For SOC Logic Design Engineer Resume
- Working knowledge of Conformal, CDC, Spyglass-LP, Spyglass-DFT, Caliber and other frontend/backend design quality check tools
- Partner with our Physical Design team on partitioning, floorplanning and timing closure
- Implement specification/design in RTL using System Verilog or System C adhering to timing/power goals
- Responsible for the logic implementation of complex design blocks using RTL coding techniques
- Proactive in seeking out work and solving problems
- Perform unit-level synthesis, including area, timing and power analysis on your unit(s)
- Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing closure, and design documentation
5
Experience For Digital Logic Design Engineer Resume
- Day to day tasks include: writing readable high performance and low power RTL and/or HLS, Synthesis and Timing closure, and design documentation
- BS or MS in Electrical Engineering, Computer Engineering, Computer Science or similar
- Proficiency with RTL coding using HDL language(s). Familiarity with circuit to convert to behavioral model, logic simulation and debug environments
- Involve in defining High Level Architecture Spec or Component Spec
- Synthesis and timing simulation of RTL designs
6
Experience For Senior SOC Logic Design Engineer Resume
- Provides consulting within knowledge domain to other team members
- Responsible for feature feasibility study, performance analysis and micro architecture of latest landing zone requirement
- Assist in the preparation of the layout design database for introduction to manufacturing
- Work with implementation to achieve your timing, area, performance and power goals
- Work with the physical design team to achieve your timing, area, performance and power goals
7
Experience For Coherency Fabric IP Logic Design Engineer Resume
- Register Transfer Level RTL coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs
- Work with physical design team to help in floor-planning of the IP block
- Work with synthesis team to close timing of the design
- In-depth understanding of DDR SDRAM operation, processor pipeline architecture, memory sub-system, cache system, and instruction set architecture
- Knowledge of external manufacturing TFMs
- Proficient with RTL Logic Design, Verification, Synthesis, DFT & STA
- Participate in the development of Architecture and Microarchitecture specifications for the Logic components
8
Experience For High Speed IO Logic Design Engineer Resume
- Involve in RTL logic design in System Verilog, Verilog and other Hardware description language
- Design and RTL implementation of logic blocks and algorithms for ASIC and FPGA implementation
- Development of requirements and interface specification of ASIC and FPGA designs
- Simulation, verification, and test bench development for RTL code designs
- Support of lab debug of designs
- Provide exceptional written and oral communication to team members
- Performs Logic design for design blocks of Soft IP SIP
9
Experience For Logic Design Engineer for High Speed Serial IO Resume
- Participates in the development of Architecture and Micro-architecture specifications for the Logic blocks
- Provides IP integration support to SoC customers and represent SIP team
- Participates in the development of Architecture and Micro-architecture specifications for the Logic components
- Works directly with partners in verification, SW, architecture and other IP partners to successfully execute on the project
- Perform logic design, Register Transfer Level RTL coding, and simulation to generate cell libraries, functional units, and sub-systems for inclusion in full chip designs
- Identify and implement RTL bug and timing fixes to support verification and structural design teams
- Own one or more logical units of the ASIC design
- Responsible for digital design of a wide variety of logic functions, with emphasis on media encoder/decoder design
- Responsible for Register Transfer Level (RTL) HDL design feasibility, development and debug
10
Experience For Logic Design Engineer Using Systemc for the Computer Vision Group Resume
- Perform logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and sub-systems for inclusion in full chip designs
- Defines and drives the development of Architecture and Micro-architecture specifications for the Logic components
- Own significant portions of the ASIC design
- Provides oversight and direction to other team members across multiple teams
- Guide/mentor, grow and develop junior engineers
- Formal Equivalence Verification FEV
- B.Sc/M.Sc in EE from one of the top universities in Israel with GPA above 85
List of Typical Skills For a Logic Design Engineer Resume
1
Skills For IP Logic Design Engineer Resume
- Experience – 8+ years of relevant work experience
- Experience in RTL design/logic design- Experience with High speed, Low Power Designs
- Good understanding of ASIC and FPGA design and implementation processes including coding, test, synthesis, and timing
- Good understanding of VLSI design, EDA synthesis tools and clock gating methodologies
- Skilled at running and analyzing lint and CDC checks
2
Skills For Senior Logic Design Engineer Resume
- Experience writing ECOs and timing assertions
- Good knowledge of RTL coding (Verilog), simulation, and verification
- Good understanding of memory types and implementation (DDR3, NVRAM, etc)
- Good understanding of communications protocols (ethernet, PCIe, SPI, I2C, etc)
- Experience with languages such as C and/or C++, SystemC, System Verilog , Perl, Shell scripting
- Experience in some of the following areas/tools: Synthesis, Formal Verification, DFT, VCS , PrimeTime, Design Compiler, Jasper, 0in. UPF
- Experience with Java, C/C++ or assembly language programming and MatLab
- Experience implementing designs with FPGAs
- Experience with Synopsis tool set - design compiler (DC), physical compiler (PC), clock tree synthesis (CTS), timing verification (PT), place and route (ICC)
3
Skills For Senior IP Logic Design Engineer Resume
- Experience with analog circuits is not required but is desired since a lot of the coding revolves around the analog design of the IO
- Experience with scripting languages e.g. Perl, shell , Python is highly desirable
- Experience in developing in System Verilog is an advantage
- Debug experience using VCS/Verdi is an advantage
- Strong knowledge of Verilog
- Strong knowledge of RTL simulators and debug
- Hardware/lab debug experience
4
Skills For SOC Logic Design Engineer Resume
- Experience with Specman/E and UVM concepts
- Industry experience in digital design of complex SoC IP blocks and products
- Experience in RTL design/logic design
- Good knowledge in design development environment
- Good knowledge in design development environments
- Experience in multiple power-domain logic design and quality checks with UPF/SPYGLASS
5
Skills For Digital Logic Design Engineer Resume
- Understanding of hardware emulation support
- Understanding of computer & platform architecture for PC, server and mobile
- Working knowledge of hardware or software architecture and design
- BS or MS in Electrical Engineering or Computer Engineering
- Comfortable working in a LINUX environment (Python, Perl, shell scripting)
- Design knowledge in the areas of floor planning, synthesis, timing, clock tree synthesis, placement and route
- Adept in programming and/or scripting (C++, Perl and others) and be conversant with flows and tools for VLSI logic design and/or functional verification
- MS in Electrical Engineering, Computer Engineering, or Computer Science
6
Skills For Senior SOC Logic Design Engineer Resume
- Well verse in interface timing budget, clock domain crossing design, and high speed IO protocol, such as PCIe or SATA
- Knowledge of computer architecture and pipelining, including major CPU sub systems
- Knowledge of synthesis, place-and-route, and statis timing analysis
- Microprocessor implementations, coding, and debug (C/C++, RTOS, ICE, etc)
- Comfortable working in a Windows environment (Word, Excel, PowerPoint, Visio)
- RTL/Logic design on ASIC's or IP blocks or SOC's using System Verilog
- Knowledge of CPU architecture; understanding of Verilog, simulator, debug
7
Skills For Coherency Fabric IP Logic Design Engineer Resume
- B.Sc. or M.Sc. in Computer/Electrical Engineering
- Control system design and performance analysis capabilities
- System Verilog/UVM verification implementation or related (OVM, VMM, assertion methodologies)
- Digital circuit design
- Board design and implementation (high speed termination, crosstalk, SSN, etc)
- Windows and Linux proficient
- Script language (Perl, Tcl) familiarity
8
Skills For High Speed IO Logic Design Engineer Resume
- An independent, motivated team player
- In design or verification of large ASICs
- Design knowledge in high speed interfaces architecture and protocols
- Experience in networking hardware design Adept in programming and/or scripting (C++, Perl and others) and be conversant with flows and tools for VLSI logic design and/or functional verification
- Hands on experience in ASIC design from RTL to GDS-II delivery for tape-in
- Experience required with System Verilog, logic design environment, execution of
- Relevant experience in ASIC design
- Relevant experiences
9
Skills For Logic Design Engineer for High Speed Serial IO Resume
- Related work experience required
- BS/MS in EE/CS with 2+ years of experience
- Relevant experiences
- BS/MS in EE/CS with 0-2 years of experience
- Experience with industry standard interfaces such as DDR, PCIE, Ethernet, USB, and CPRI
- BSc. EE or Computers
10
Skills For Logic Design Engineer Using Systemc for the Computer Vision Group Resume
- In-depth knowledge of advanced verification flow (constrained random, assertion, functional coverage, code coverage)
- Exposure in low power design. Familiarity with TLMs
- Exposure to low power design
- Experience in performing logic design, Register Transfer Level RTL coding, and the development of Architecture and Micro-architecture specifications for the Logic components
- Experience in collaborating with Pre-silicon validation, Architecture team to achieve full coverage validation strategy/design scoping plan on the new feature set, and even leading new feature set execution
- Experience in analyzing and driving design flow/tools flow methodology/coverage validation activities across projects horizontally
- Experience in USB/PCI express or any High Speed Serial I/O protocol is highly desired
List of Typical Responsibilities For a Logic Design Engineer Resume
1
Responsibilities For IP Logic Design Engineer Resume
- Course work focused on design of analog, digital, and power circuitry, with solid understanding of underlying theory and principles
- Strong knowledge in Logic Synthesis, Timing Analysis, Timing closure and UPF
- Familiarity or experience with RTL verification and timing analysis/closure is required
- Function independently while maintaining strong team-work and collaborative approach
- Experience with ouArchitecture Development and Design Tradeoff Analysis, RTL Coding, Design Reviews, SYN, CDC, FEV, DFT insertion, ATPG analysis,
- Experience in the area of DSP, multi-threading, caches, memory controller, Interfaces -OCP, AXI, PCI either as hardware design or verification
- Logic validation, synthesis, and timing analysis tools
2
Responsibilities For Senior Logic Design Engineer Resume
- Working level mastery of Unix based design environment, industry standard digital design tools, scripting languages and ASIC flows
- Understanding of Transmission line application and High Speed Design techniques
- Knowledge of Intel Architecture ISA and system architecture, including x86 assembly language
- Self-starter. Ability to take the lead in managing one's career
- Circuit design Computer architecture TCL, Perl and/or C++ programming
- Passion for technology, commitment to driving results and ability to get into the details
- Well versed with Micro-architecture design, RTL coding with Verilog/System Verilog and or System-C
- Capability using laboratory equipment such as logic analyzers and
- Mentor junior members of the team and improving the overall technical bench strength of the organization
3
Responsibilities For Senior IP Logic Design Engineer Resume
- Write readable high-performance, area and power efficient RTL to achieve your design targets
- Provide design documentation for your design
- Integration and Infrastructure support and development
- Collaborate with our verification team to verify the correctness of your unit
- Familiarity with Very Large-Scale Integration VLSI Complementary Metal-Oxide Semiconductor CMOS logic Design
- RTL Verilog, or SystemVerilog with a working knowledge of hardware modeling issues and logic debug environments - Modern energy-efficient/low-power logic design techniques, including those specifically applicable to high frequency optimization
- Working knowledge of Industry standard circuit design tools, including schematic capture, logic synthesis, place and route, static timing analysis and design closure -Scripting in Perl, Python, Ruby, TCL, or some other scripting language
- Strong communication and collaboration skills, including a willingness to work with others, and the ability to tolerate ambiguity and highly complex decision environments. Able to lead small work group to complete mega tasks at IP or SOC level
4
Responsibilities For SOC Logic Design Engineer Resume
- Experience in:Verilog, DC, PTSystem VerilogC/C++ & scripting Protocols: AHB, Ethernet, PCIE is an advantage
- Experience in chip design
- Industry experience in IP and SoC design
- Familiarity with circuit planning and physical layout
- High speed circuit design and optimization for analog, mixed signal, special circuits and/or, large/small signal arrays
- Experience in digital logic design with various tools and methodologies including: System Verilog, Perl, VCS/Synopsys simulators, Lint, Synthesis, Clock Domain Crossing tools, DFX Scan and Power
5
Responsibilities For Digital Logic Design Engineer Resume
- Motivated, self-directed, and able to work effectively both independently and in a team environment
- BS or MS in Electrical Engineering, Computer Engineering, Computer Science or similar- 6 years of experience in logic design or related experience
- Experience CPU design and or verification
- Experience in PC Architecture
- Experience in digital logic design with various tools and methodologies including: System Verilog, Perl, VCS/Synopsys simulators, Lint, Synthesis, Clock Domain Crossing tools, DFX Scan and Power
- Hands-on experience with
- Broad experience in Very Large Scale Integration VLSI and Microprocessor or ASIC/SoC design methods
- Experience in fabric switch/NIC design
6
Responsibilities For Senior SOC Logic Design Engineer Resume
- Experience with internal and external logic design tools and flows
- Experience with ASIC teams through all phases of development
- Experience with micro-architecture and RTL design,
- Experience with computer system architecture
- Experience in Virtualization, I/O interface architecture
- Experience with PCI Express Technology
- Knowledge of critical PC IO subsystems e.g PCIe, USB, SATA, UART, SPI
- Knowledge of IO Controllers and Design and worked with standard buses / bridges such as AHB / OCP / AXI
7
Responsibilities For Coherency Fabric IP Logic Design Engineer Resume
- Knowledge of Low power / High Performance Designs and Practices
- Logic Design or Pre-Silicon Verification
- Skills pertaining to Pre-Silicon Logic Design, including expertise in: System Verilog for Design, Logical Synthesis, STA, Timing closure, Linting, Desing for Low Power techniques and Verification skills such as: test development, execution, debug
- Experience in networking hardware design
- Experience with running, debugging and interpreting quality tool flow and outputs Formal verification, clock crossing checks, timing exception verification, DC, Linting tools, etc
- Experience with Monitoring and/or Test & Measurement tools. Experience with one or more of the following protocols: PCIe, USB, SAS, SATA, Ethernet, Fibre Channel, Thunderbolt
- Experience in logic design
- Logic design using System Verilog Micro-architecture trade-offs and documentation
8
Responsibilities For High Speed IO Logic Design Engineer Resume
- Familiarity and experience in PCIe protocols, Cache-coherence protocols, on-chip Interconnect fabrics, Multi-clock domain design, IOSF Sideband and Chassis State machine design
- Knowledge of fabric switch/NIC design
- Knowledge of internal and external logic design tools and flows
- Knowledge of Finesim, VCS, Co-sim, Conformal LEC is an advantage
- Experience in digital logic design with various tools and methodologies including: System Verilog, Perl, VCS/Synopsys simulators, Lint, Synthesis, Clock Domain Crossing tools, DFX Scan and/or Power
9
Responsibilities For Logic Design Engineer for High Speed Serial IO Resume
- Experience with High Speed I/O Design, Mixed Signal Design or Validation Experience with CDC, Lint, UPF, or GLS
- Strong Design Development Skills (Verilog, System Verilog or VHDL)
- Highly motivated individual with strong interpersonal skills
- Strong background in computer architecture programming experience in system Verilog, Perl
- Experience in leading a team of engineers in Compression RTL design and Validation
- Experienced logic designer - at least 5 years’ experience
- Experience with front-end design tools, 10nm tools, flows and methodology, covering RTL simulation/debug, Lint, Clock Domain Crossing and timing exceptions
- Experience in System Verilog RTL coding of one or more Soft IPs
10
Responsibilities For Logic Design Engineer Using Systemc for the Computer Vision Group Resume
- Proven track record of developing first-time-right SoCs to meet aggressive development schedules
- Experience/knowledge of Ethernet protocols and accelerators for networking & storage
- Experience with common lab bench top equipment (scopes, DMMs, function generators, etc.)
- Familiarity or experience in RTL design with Verilog and/or VHDL is required
- Work experience in the semiconductor industry
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