Design Verification Resume Sample

15 votes
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Beau Davis
44636 Sedrick Ferry,  Boston, MA
+1 (555) 466 5802

Work Experience

SSD Design Verification Lead
07/2015 - PRESENT
Los Angeles, CA
  • Knowledge of Verilog/System Verilog, digital simulation and debug is required
  • Exposure to UVM is desired
  • Design verification experience in micro-processor design, with programming ability in C, C++, System C and System Verilog
  • Capable of building a high performing team, including selection, development and deselection, to deliver the results required from the organization
  • Hire and Develop the Best: hire the industry’s best talent and mentor, build expertise, and grow each team member
  • Co-op/interns participate on projects related to delivering HPE's next- generation high performance server products
  • M.Tech/M.S with 10+ years of experience in digital design / design verification
Smts, IC Design Verification
12/2012 - 02/2015
Boston, MA
  • Proficient in System Verilog, C++, Python/Perl
  • 3rd year B.Sc student of Computer Engineering or Electrical Engineering
  • Computer Engineering Fundamentals Knowledge
  • Good communication skill, willing to learn & explore new areas
  • Motivated to continuously develop skills and accept a variety of responsibilities as part of contributing to the team’s success
  • Enthusiastic, flexible with strong inter-personal skills
  • Months of experience with SW programming expertise in: C, C++ or System Verilog
  • Months of experience with SW programming expertise in : C, C++, or SystemVerilog
Design Verification Intern
01/2007 - 06/2012
Philadelphia, PA
  • Prior experience with design verification at block and system level
  • Learn the architecture and micro architecture by studying specifications and direct interaction with architects and logic designers of the CPU
  • Develop test plans, test benches and tests, creating sequencers, drivers, checkers, and monitors in a UVM environment
  • Enhance test benches and tests to achieve coverage goals
  • Apply formal methods to supplement stimulus based verification
  • Create and support test environments for different design hierarchy levels
  • Support unit and super-unit debug on simulation and emulation platforms
  • Developed test plans of complex systems containing multiple state machines and protocol rules
  • Composed functional coverage assertions, preferably using system Verilog


International Technological University
2002 - 2007
Engineer's Degree in Electrical Engineering

Professional Skills

  • Strong debugging skill using GDB and Valgrind
  • Strong skill in modeling with floating point arithmetic, parametrized precision
  • Collaborative and good communications skills
  • Acquires and applies job skills and learns the company policies and procedures to complete assigned tasks that are routinely/semi-routinely in nature
  • Experience with integrating model with Verilog, co-simulating and debugging in an integrated environment
  • Strong knowledge in C/C++ based modeling in the domains of signal processing, system performance and memory management
  • Experience in defining and building modular architecture of a model based on a system architecture/design specifications

How to write Design Verification Resume

Design Verification role is responsible for modeling, communications, assembly, design, reporting, architecture, credit, digital, languages, english.
To write great resume for design verification job, your resume must include:

  • Your contact information
  • Work experience
  • Education
  • Skill listing

Contact Information For Design Verification Resume

The section contact information is important in your design verification resume. The recruiter has to be able to contact you ASAP if they like to offer you the job. This is why you need to provide your:

  • First and last name
  • Email
  • Telephone number

Work Experience in Your Design Verification Resume

The section work experience is an essential part of your design verification resume. It’s the one thing the recruiter really cares about and pays the most attention to.
This section, however, is not just a list of your previous design verification responsibilities. It's meant to present you as a wholesome candidate by showcasing your relevant accomplishments and should be tailored specifically to the particular design verification position you're applying to. The work experience section should be the detailed summary of your latest 3 or 4 positions.

Representative Design Verification resume experience can include:

  • Experience with creating a detailed verification plan
  • Proven expertise in Silicon and FPGA based product development
  • Valid Work Permit
  • DC-DC Power solutions testing and debugging
  • Bachelors or Masters in Electronics & Communication Engineering / Electrical Engineering/Computer science from a reputed college / university
  • Hebrew & English fluent speaking and writing

Education on a Design Verification Resume

Make sure to make education a priority on your design verification resume. If you’ve been working for a few years and have a few solid positions to show, put your education after your design verification experience. For example, if you have a Ph.D in Neuroscience and a Master's in the same sphere, just list your Ph.D. Besides the doctorate, Master’s degrees go next, followed by Bachelor’s and finally, Associate’s degree.

Additional details to include:

  • School you graduated from
  • Major/ minor
  • Year of graduation
  • Location of school

These are the four additional pieces of information you should mention when listing your education on your resume.

Professional Skills in Design Verification Resume

When listing skills on your design verification resume, remember always to be honest about your level of ability. Include the Skills section after experience.

Present the most important skills in your resume, there's a list of typical design verification skills:

  • Work effectively with internal designers and external contractors in different time zones
  • Strong interest in hardware design and/or verification
  • Experience in a related role
  • Experienced with assertion based methodologies
  • ASIC design, verification, or related work experience
  • Relevant Verification experience

List of Typical Skills For a Design Verification Resume


Skills For Design Verification Intern Resume

  • Regression management and verification closure reporting
  • Coursework in Digital logic, computer architecture, software engineering, and/or data structures
  • Available to work the September through December term
  • Available to work the January through April work term
  • Coursework in VLSI design or concepts, and/or analog VLSI design or concepts
  • Commitment, self-motivation, and the ability to work in a team-oriented environment are essential
  • Knowledge of digital design verification including test environment implementation and test plan development Knowledge of C, System Verilog and/or other verification languages and simulators

Skills For SSD Design Verification Lead Resume

  • Available to work the 4 month work term
  • Knowledge in Computer Architecture, Digital Design and Verifiction
  • Knowledge in data structures and algorithms, digital logic, digital test and verification, assembly language, and familiarity with hardware description languages
  • MS in EE or CE with VLSI emphasis. Graduate from reputable university with competitive GPA or
  • Analysis of analog DC/DC power designs

Skills For Smts, IC Design Verification Resume

  • Architect a re-usable and scalable verification environment
  • Expert in all aspects of UVM based verification methodology
  • Highly knowledgeable in coverage extraction, creation and implementation
  • Apply verification methodology to create re-useable verification IP
  • Academic score 60% and above
  • Normally follows established procedures on work. Requires instructions on tasks
  • AND --
  • Work closely with the design team to review specifications and architecture, extract features, define modeling plan, framework Defining, building and debugging C/C++ based transaction level model Integrate model with the design and test benches and simulate with Verilog simulators Build model debug infrastructure using GDB/Valgrind or with Simulator

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