Design Enablement Resume Sample

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Enid Gusikowski
3730 Aubrey Creek,  Boston, MA
+1 (555) 142 1104

Work Experience

Senior Eng Design Enablement
05/2017 - PRESENT
Detroit, MI
  • Design and implementation of Silicon PA and RF Power component prototypes
  • QA of Process Design Kit elements, including device library, DRC, LVS, PEX runsets and Device Libraries
  • Review release notes and application notes
  • Characterize initial silicon and work with external test resources for comprehensive testing of sufficient quantities of ICs to demonstrate achievement of critical performance requirement. Also document all the design, measurements and correlation silicon vs simulation
  • Perform root cause analysis of printing and yield limiting hotspots using proven tools
  • Design and assemble patterning test masks used for process development and OPC model calibration
  • Day to day interaction with various development teams and developing and debugging test structures within internal regression testing flow
Smts Design Enablement
05/2012 - 01/2017
Phoenix, AZ
  • Develop a mapping/interface files to enable smooth extraction flows from LVS to PEX
  • Work with QA team to improve quality of deliverables
  • Develop automation to improve efficiency
  • Provide information to customer support engineers for customer issue resolution
  • Good understanding of the device physics of SOI and bulk CMOS RF transistors and the correlation of the process technologies to the transistors’ RF performance. The key Figure-of-Merits of interest include Ft, Fmax, 1/f noise, HF noise, IIP3, OIP3, P1dB etc
  • Create and maintain testcases for GLOBALFOUNDRIES RF transistor models integration into PDK kits, perform simulations and physical quality assurance checks to ensure error free PDK kits delivery to customers. Run customer’s RF transistor testcases/netlists for model QA/de-bugging
  • To develop Parasitic Extraction technology files to support GF Technologies
Design Enablement Intern
11/2007 - 04/2012
San Francisco, CA
  • Be able to lead a project team to complete a full-scale test chip development, from plan to tape-out
  • PhD or Masters in Electrical Engineering or Physics
  • Industry experience and expertise in CMOS device physics, Advanced Semiconductor Manufacturing process and IC design
  • Spec, Scope, create and maintain dummy generation enablement for PDK’s
  • Develop and maintain OPC code (recipe) for various technodes
  • Develop and maintain ORC code (recipe) for various technodes
  • Work on different aspects of OPC code - like SRAFs, MRC, Booleans
  • Do ORC review with required details and complete within agreed time
  • Engineering with 12 years of experience


Auburn University
2002 - 2006
Engineer's Degree in Electrical

Professional Skills

  • Demonstrate excellent coding skills (Unix/perl/Makefiles/tcl/skill)
  • Excellent Debugging skills (Back End, Simulation, parasitic extraction)
  • Highly operational and strong execution skills, takes initiative and independent
  • Good interpersonal skill, tactful, resourceful, possess initiative, good presentation skills
  • Coding experience with VisualBasic in Excel is a strong benefit
  • Programming skills: p-cell, Python/Perl, shell scripts
  • M.S. with 7 years of experience, or PhD with 5 years’ experience

How to write Design Enablement Resume

Design Enablement role is responsible for coding, planning, integration, database, printing, shipping, architecture, reporting, manufacturing, design.
To write great resume for design enablement job, your resume must include:

  • Your contact information
  • Work experience
  • Education
  • Skill listing

Contact Information For Design Enablement Resume

The section contact information is important in your design enablement resume. The recruiter has to be able to contact you ASAP if they like to offer you the job. This is why you need to provide your:

  • First and last name
  • Email
  • Telephone number

Work Experience in Your Design Enablement Resume

The section work experience is an essential part of your design enablement resume. It’s the one thing the recruiter really cares about and pays the most attention to.
This section, however, is not just a list of your previous design enablement responsibilities. It's meant to present you as a wholesome candidate by showcasing your relevant accomplishments and should be tailored specifically to the particular design enablement position you're applying to. The work experience section should be the detailed summary of your latest 3 or 4 positions. Representative Design Enablement resume experience can include:

  • The individual would require to interpret process design rules, spice model, and interconnect specifications and electrical parameter documents, to create specification data for PEX deck development
  • Experience developing automation and scripting using languages such as Tcl, Perl, etc
  • Develop engineering scripts for automating custom (Analog/RF) design flow in Virtuoso to validate model based results with silicon measurement data
  • Education – M.S. in Electrical Engineering, Materials Science, Solid State Physics, or other relevant engineering or physical science discipline
  • Masters in Electrical Engineering or Physics with 10+ years of experience
  • Very good understanding of process technology, digital design, and digital implementation and analysis EDA tools and flows

Education on a Design Enablement Resume

Make sure to make education a priority on your design enablement resume. If you’ve been working for a few years and have a few solid positions to show, put your education after your design enablement experience. For example, if you have a Ph.D in Neuroscience and a Master's in the same sphere, just list your Ph.D. Besides the doctorate, Master’s degrees go next, followed by Bachelor’s and finally, Associate’s degree.

Additional details to include:

  • School you graduated from
  • Major/ minor
  • Year of graduation
  • Location of school
These are the four additional pieces of information you should mention when listing your education on your resume.

Professional Skills in Design Enablement Resume

When listing skills on your design enablement resume, remember always to be honest about your level of ability. Include the Skills section after experience. Present the most important skills in your resume, there's a list of typical design enablement skills:

  • Bachelors in Electrical/Electronics engineering with 2+ years of experience. Good aptitude in programming and understanding of basic circuits
  • M.S. with 10 years of experience, or PhD with 8 years’ experience
  • Software Engineering Programming Languages (Java, Perl) and scripting language (Korn Shell) on a Linux platform and relational database experience
  • Solid understanding of RF technology device engineering and processing, and device physics
  • Ph.D. in Electrical Engineering, Materials Science, Solid State Physics, or other relevant engineering or physical science discipline
  • Experience creating and debugging JSON files

List of Typical Experience For a Design Enablement Resume


Experience For Smts Design Enablement Resume

  • Relevant experience with a solid understanding of semiconductor processes, devices and their layout
  • Good EDA tool scripting and automation experience (TCL, Perl, Make)
  • Develop regression test-cases for DRC/LVS/PEX components, validate coverage for all supported vendor tools
  • Knowledge of semiconductor physics and application in understanding device data (Diode, Varactor, MOSFET etc.)
  • Knowledge of S-parameters and their application in extracting device models
  • Bachelors in Electrical Engineering, Microelectronics, or equivalent
  • Develop PEX decks to support the major PEX tools (Cadence QRC, Mentor xRC & Synopsys StarRC) used by customers
  • Create and maintain test cases for PEX decks and perform quality assurance checks to ensure error free deliveries to customers

Experience For MTS Design Enablement Resume

  • Validate PEX decks integration with device library and layout-vs-schematic runset+spice models for post-layout simulation to ensure proper integration of process design kit components
  • PEX decks regression based on in-house bench-mark designs and correlate results with hardware
  • Create and update release notes and application notes, and to document any known limitations, issues, and solutions, in order to communicate relevant information on proper usage of the Process Design Kit components to GF customers
  • Develop & create DRC regression pass/fail test-cases based on ground design rules specification
  • Through validation of all components of PDK (compact-model verification, complete front-end device, simulation, p-cell to back-end physical design verification) before shipping kits to customers
  • Masters in Computer Science, Electrical Engineering, Physics, Computer Engineering or related field with 7 years exp

Experience For Senior Eng Design Enablement Resume

  • To develop top level PDK release notes for customers
  • To package and release high quality PDKs
  • To work closely with the PDK infrastructure team and IT to optimize and enhance the PDK release process
  • Expertise in device physics and with SPICE level simulators such as HSPICE, SPECTRE
  • The evaluation, development and management of new feature integration in advanced node PDKs
  • Work independently in an international team, to drive project definition, execution, and delivery is highly desirable

Experience For Pmts Design Enablement Resume

  • Deep hands-on experience with digital implementation tools and flows (i.e. Synopsys ICC/ICC2, Cadence EDI/INNOVUS) including RTL synthesis, place and route, parasitic extraction, static timing, power and EMIR analysis (Synopsys, Cadence, Apache) and physical verification (Mentor, Synopsys, or Cadence) for advanced technologies like 28nm through 7nm
  • Strong knowledge in design closure preferably gained by work on at least one full chip tape-out, including block closure for timing and performing logical and physical ECO
  • Low power design techniques and UPF (IEEE 1801)
  • Understand liberty (.lib) formats (NLDM, CCS, ECSM, AOCV/POCV/LVF)
  • Close gaps between customer needs and specifications
  • Act as single contact window between the SSD team and IT
  • Perform overall coordination for system development activities

Experience For Design Enablement Engineer Resume

  • Passionate about strategy formulation and embrace automation solutions
  • Possesses an analytical mind
  • Learn how to use ExcelDM (an internal Excel extension) to maintain and modify device truth tables
  • Update truth tables for compatibility with Datamart (an internal database)
  • Learn to recognize active portions of electronic devices in design
  • Update regions definitions so that a computer can correctly recognize active portions of electronic devices in design
  • Support regional sales teams to represent FIP offerings
  • Leading small to large teams of circuit designers / IP developers in the use of Cadence and Synopsysis tools for Standard Cell, Input/Output, and Compiled Memory circuit designs
  • Own interface to broader GLOBALFOUNDRIES Engineering Design Automation, Technology Development, and Physical Design Kit teams for design tool support and problem resolution

Experience For Princ Eng Design Enablement Resume

  • Experience – At least 11 years of experience with any transistor level EDA design, simulation, and analysis tools
  • Develop frame validation automation scripts
  • BS Student enrolled in an accredited program on Electrical Engineering, Computer Engineering, Software Engineering, Computer Science, Physics, or related fields
  • Run Frequency sweeps on digital designs to correlate between different steps of flow from Synthesis to final signoff
  • Develop process design rules with the objective to balance process capabilities and maximization of the design application space
  • Develop methods and software tools to improve Ground Rule development efficiency or accuracy
  • Design and layout of device test structure and definition of electrical tests and data acquisition

Experience For Design Enablement Intern Resume

  • Extraction of model parameters from characterization data
  • Creation of and responsibility for model documentation
  • Familiarity with standard compact models such as BSIM, BSIMSOI, PSP, VBIC, HiCUM, or the VerilogA language
  • Research and source for vendors & IP Solutions to meet market requirement
  • Involve in vendor selection process through assessment of capability, TAT, quality, etc
  • Formulate the IP development project plan with IP ecosystem partners

Experience For Smts Pathfinding Design Enablement Resume

  • Deep hands-on experience with digital implementation tools and flows (i.e. Synopsys ICC/ICC2, Cadence EDI/INNOVUS, or Mentor OlympusSoC) including RTL synthesis, Place and Route, parasitic extraction and static timing (Synopsys or Cadence) and/or physical verification (Mentor, Synopsys, or Cadence) for advanced technologies like 28/16/14/10nm
  • Assess and define IP Impact Assessment plan based on PDK update
  • Perform IP Regression (Physical verification DRC/LVS/DFM, PEX extraction and Spice simulation) against predefined passing criteria and meeting committed cycle time
  • Consolidation and review of IP Assessment results
  • Hands on experience in industry standard CAD tools
  • Good attention to detail, Well organized and work well within a team environment
  • Experience with design tools and/or physical layout
  • Capability to use circuit and other CAD simulation tools such as ADS, GoldenGate and spectreRF for effective simulation
  • Experience with silicon, GaAs and/or GaN technologies

Experience For Principal Eng Design Enablement Resume

  • Relevant experience, 5 years with Master’s, or 3 years with a PhD
  • Academic research experience
  • Experience in electro-magnetics, parasitic extraction, or device physics
  • Development experience in parasitic extraction decks (Synopsys
  • Experience with field solvers (e.g. Raphael, FastHenry, QuickCap, or similar tool)
  • Chair meeting / review with all stakeholders for impact seen on the IP and drive to closure
  • Support customer queries and resolve technical issues related to IP

Experience For Senior Engr, Design Enablement Resume

  • Maintain and manage IP Regression Database
  • Maintain and improve regression automation scripts to enhance work efficiency
  • Continuous improvement in test case suite to ensure high coverage for IP
  • Documentation of IP technical issues, waiver documents and assessment report
  • Maintain ISO SOP workflow documentation and preparation for audit
  • Technically sound in circuit design and simulation
  • Knowledge in IC process and layout design
  • Device model extraction for DC and RF frequencies (BSIM/PSP and their SOI versions as required)
  • Definition of test structures and layout as and when necessary

List of Typical Skills For a Design Enablement Resume


Skills For Smts Design Enablement Resume

  • Masters in Computer related field, or Engineering related field with 8 years of experience
  • Experience of direct customer facing, support role
  • Strong programing knowledge and knowledge of Python and Cadence
  • Good aptitude for analytical problem-solving, and a keen orientation for details
  • Device or circuit simulation experience using Cadence and/or ADS
  • Experience in chip tape-out and chip bring-up

Skills For MTS Design Enablement Resume

  • Receive customer service requests and questions, screen, categorize, prioritize and assign to internal support groups
  • A combination of hands-on work experience of 1-2 years; 2 years Post Doc work, and 3 + years of research work in an academic setting
  • Hands on experience in TCL, Perl and shell programming
  • Experience working with semiconductors
  • Knowledge of and experience with the most common peripherals used in the embedded world PCIe, Ethernet, ..
  • Experience in applied application of semiconductor device physics
  • Experience with design tools and/or physical layout
  • Good knowledge of EDA tools and CAD environment setup is required
  • Experience with Cadence transistor level EDA design, simulation, and analysis tools

Skills For Senior Eng Design Enablement Resume

  • Experience with Cadence Virtuoso for custom design and Innovus/ICC/ICC2 for Digital design
  • Hands on experience with DRC/LVS/PEX
  • Experience with documentation software, e.g. Framemaker
  • Work experience in circuit design, PDK development, or related EDA industries
  • Experience in circuit applications such as RF switch, power amplifier, or low noise amplifier circuits
  • Experience with industry standard EDA tools for memory design and analysis from Cadence/Mentor/Synopsys
  • Validate the decks for Resistance, Capacitance and Inductance with respect to Field Solvers (Raphael, FastHenry, QuickCap)
  • FIP FAE experience is preference
  • Engineer and validate rules via statistical analysis, interlock with others, such as Device engineers, Process integration engineers, Pcell and DRC developers

Skills For Pmts Design Enablement Resume

  • Experience in IC Design Project management or other IP-related domains
  • Good Semiconductor process technology knowledge
  • Understanding of test engineering, test equipment (ATE) and test operations
  • Understanding customer’s needs and translating requirements into specifications for IT development
  • Responding and closing customer FIP requirements
  • Directing the work of colleagues and mentoring new hires
  • Understanding of semiconductor device, design flows, methodologies and variation margins
  • Benchmarking the power, performance and area (PPA) of new GLOBALFOUNDRIES technologies with respect to specific market segments

Skills For Design Enablement Engineer Resume

  • Developing regional FIP sales collateral
  • Providing regional market intelligence of FIP needs for targeted customers and application segments
  • Enabling digital and analog circuit design and development with industry standard Synopsys and Cadence EDA tools
  • Benchmarking the power, performance and area (PPA) of new GLOBALFOUNDRIES technologies
  • Modeling Test structure development for
  • MS, Electrical Engineering, Computer Engineering, or other relevant engineering discipline

Skills For Princ Eng Design Enablement Resume

  • Implementation of digital SoC building blocks from RTL synthesis to GDS sign-off including timing, power, and area optimization
  • Help in evaluation, benchmarking, design in and bring up of IP products
  • PhD in Electrical Engineering, Physics, or related Engineering field
  • M. Tech. / MS in Electrical Engineering, Physics, or Computer Engineering
  • Knowledge of programming (JSP, Spring framework, JavaScript/Dojo, LDAP, AJAX, Rest Services, JBoss, CSS and LSF)
  • MS enrolled in accredited Electrical Engineering, Computer Engineering or Physics Program

Skills For Design Enablement Intern Resume

  • Develop engineering scripts to automate power grid mesh and custom routing
  • Familiar with RF characterization and modeling softwares such as Agilent’s ICCAP and ADS
  • Understand and communicate customer IP requirements to design and marketing teams
  • BS or Masters in Electrical Engineering or Physics
  • Knowledge of device physics or semiconductor device engineering

Skills For Smts Pathfinding Design Enablement Resume

  • Basic use of Assura or Calibre DRC checking tools
  • Close collaborating with design methodology, PDK development, and physical IP development teams as well as EDA vendors
  • Familiar with advanced semiconductor manufacturing, device and circuit layout, or dataprep and tape out procedures
  • Evaluate existing resources and systems
  • Provide complete solutions to customers, thereby reducing system setup time
  • Builds unprecedented data analysis, administrative and reporting tools to increase efficiency of resource deployment and work progresses
  • Enthusiastic about continual improvement activities, inquisitive and willing to contribute knowledge

Skills For Principal Eng Design Enablement Resume

  • Schematic and Layout extraction / netlist generation using Cadence and Synopsysis tools
  • Circuit simulation for verification of design using Cadence and Synopsysis tools
  • Physical and electrical circuit design rule generation (Verilog, Lef, cdl, gds, .lib, etc) using Cadence and Synopsysis tools
  • Document design rules using standardized methods and formats
  • Development of compact device models including subcircuit definition and enhancements to industry standard models
  • Definition of model quality standards and checking to those standards
  • Responsible for continuous improvement of model functionality and modelling methodology
  • Background in device characterization techniques (including DC, S-Parameter, nonlinear RF characterization) and parameter extraction

Skills For Senior Engr, Design Enablement Resume

  • Manage IP Ecosystem Partners IP development programs with help from internal supporting resources
  • RTL2GDS flow creation and qualification for Synthesis, Place and Route, Extraction, Timing and Physical Verification
  • Develop low power flow techniques using UPF and other industry standard solutions
  • Familiar or has worked on foundry’s PDK and usage for deep submicrometer and/or nanometer testchip tapeouts
  • Interface with customers to support integration of IP into customer designs

List of Typical Responsibilities For a Design Enablement Resume


Responsibilities For Smts Design Enablement Resume

  • Design experience in standalone and integrated power amplifiers for designs operating in the RF, microwave and millimeter wave bands
  • Interaction with team to resolve discrepancies in the data, model etc
  • Familiarity with 3GPP and /or 802.11 specifications
  • Able to perform physical quality assurance checks of RF model kits at the netlist level and in custom design environment to ensure error free PDK kits delivery to customers. Run customer’s RF testcases/netlists for model QA/de-bugging
  • RF exp
  • Meet tight deadlines, commitments and deliver
  • Relevant experience in Semiconductor IP/Library Design (standard cells, memories, I/O’s, Analog Blocks, PHY/Serdes), preferably as a former design or applications engineer

Responsibilities For MTS Design Enablement Resume

  • Hands-on experience with on-wafer DC/AC/RF/noise/large-signal characterization and de-embedding procedures using Cascade Microtech prober, Agilent’s PNA, PLTS etc
  • Good knowledge of SOI and bulk CMOS semiconductor processes for RF technologies on 12, 14, 22, 28, 40, 55, 65, 130 and 180nm nodes
  • Experience with design tools and/or physical layout
  • Academic research
  • FDSOI and Advanced FinFET Logic Technologies
  • Familiarity with foundry technologies
  • Familiarity with 3GPP 5G and other relevant specifications

Responsibilities For Senior Eng Design Enablement Resume

  • Work with early release PDKs and technologies
  • Knowledge of commercial software (GOOGLE Apps, Cadence K2 Mask Compose)
  • Self motivated, able to take ownership of assignments
  • Knowledge in Spice simulations (HSPICE, Spectre)
  • Familiarity with automation software such as ICCAP and Matlab

Responsibilities For Pmts Design Enablement Resume

  • Demonstrate strong presentation, and communication, skills to present the capabilities of Intel’s product portfolio, and perform demonstrations of feasibility studies, and proofs of concept, in customer meetings and seminars
  • Understand test structures / IP/ macro fully; be able to provide technical support/guidance to other engineers
  • Create and update model release notes, model reference documents and application notes. Document any known limitations, issues, and solutions, in order to communicate relevant information on proper usage of the RF transistor model kits to GLOBALFOUNDRIES’ customers
  • Answer customer questions on IP products or re-assign to internal IP support groups
  • Leverage the IP Management System to track all customer IP deliveries, updates, service requests, open and closed cases
  • Interface with customers to gather regular feedback on INVECAS IP products, score card, service quality and customer satisfaction
  • Gather from customers and report on market intelligence, new product requests, competitive moves, IP PPA competitiveness, new industry standards, etc. to drive new IP product development or improvement

Responsibilities For Design Enablement Engineer Resume

  • Attend relevant industry standard committee meetings to learn about upcoming changes or new standards to help INVECAS develop new competitive IP products ahead of competition and to be the spokespersons of INVECAS therein
  • Develop relevant technical seminar material, webinars, videos, demo systems showcasing INVECAS IP at trade shows, events, etc
  • Experience – long lasting years of semiconductor device or process integration experience; Good understanding of device truth table, mask generation rule/Boolean; Solid understanding of semiconductor device physics, process integration, design rule definitions; Able to use design tools to view layout design and run DRC checks for design rule evaluations

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